- cross-posted to:
- technology@midwest.social
- technology@lemmy.ml
- cross-posted to:
- technology@midwest.social
- technology@lemmy.ml
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According to data published in Huawei’s research paper, the Kirin 2026 adopts dual-layer Logic Folding, which increases transistor density from 155 million transistors per square millimeter (155 MTr/mm²) to 238 million transistors per square millimeter (238 MTr/mm²), a gain of around 53.5% over the 2025 Kirin 9030 Pro baseline.
HOLY FUCK, that’s a huge jump!
Yeah wow. My understanding is that physically moving electrons around is the biggest energy sink (and this heat source) in a computer chip, and that’s why (or part of why) smaller transistors directly corresponds to higher energy efficiency, there’s less distance for them to travel.
Stacking into two layers hypothetically has a very similar effect and it looks like we’re finally going to see it in effect. Neat!
